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? semiconductor components industries, llc, 2014 february, 2014 ? rev. 13 1 publication order number: nois1sm1000a/d nois1sm1000s, nois1sm1000a star1000 1m pixel radiation hard cmos image sensor features ? 1024 x 1024 active pixels ? 15 m x 15 m pixel size ? 1 inch ? 35 mm optical format ? high radiation tolerance ? high sensitivity ? low noise ? monochrome and color ? 11 frames per second (fps) at full resolution ? on-chip 10-bit analog-to-digital converter (adc) ? region of interest (roi) readout ? windowed and subsampled readout ? rolling shutter ? on-chip fixed pattern noise (fpn) correction ? ceramic jlcc-84 package ? bk7g18 glass with n2 filled cavity ? 400 mw power dissipation ? these devices are pb ? free and are rohs compliant applications standard market applications ? nuclear inspection space applications ? space science ? star trackers ? sun sensors itar information ? the star1000 is an itar ? free component description the star1000 is a cmos image sensor with 1024 by 1024 pixels on a 15 m x 15 m pitch. it features on-chip fixed pattern noise (fpn) correction, a programmable gain amplifier, and a 10-bit analog-to-digital converter (adc). all circuits are designed using the radiation tolerant design techniques to allow high tolerance against radiation effects. registers which contain the x- and y- addresses of the read out pixels can be directly accessed by the external controller. this architecture provides for flexible operation and allows different operation modes such as (multiple) windowing, subsampling, and so on. the star1000 is assembled using a bk7g18 glass lid with a nitrogen-filled cavity which increases the temperature operating range. the star1000 flight model has additional screening to space qualified standards. ordering information marketing part number description status package nois1sm1000a-hhc mono with bk7g18 glass, engineering model production 84 pin jlcc case 114ak nois1sm1000s-hhc mono with bk7g18 glass, flight model nois1sm1000a-hwc mono windowless, engineering model nois1sm1000s-hwc mono windowless, flight model risk production NOIS1SC1000A-HHC color with bk7g18 glass, engineering model engineering http://onsemi.com figure 1. star1000 in 84 ? pin ceramic jlcc package jldcc84 case 114ak
nois1sm1000s, nois1sm1000a http://onsemi.com 2 ordering code decoder marking the marking shall consist of a lead identification and traceability information. lead identification an index to pin 1 shall be located on the top of the package as shown in section package dimensions on page 21. the pin numbering is counter clock-wise, when looking at the top-side of the component. traceability information tests each component shall be marked such that complete traceability can be maintained. the component shall bear a number that is constituted as follows: orderable part number package mark: line 1 package mark: line 2 package mark: line 3 nois1sm1000a-hhc nois1sm1000a -hhc nnnn awlyyww nois1sm1000s-hhc nois1sm1000s -hhc nnnn awlyyww nois1sm1000a-hwc nois1sm1000a -hwc nnnn awlyyww NOIS1SC1000A-HHC* nois1sc1000a -hhc nnnn awlyyww where nnnn- serialized number controlled manually by on semiconductor, belgium where awlyyww represents the lot assembly date *the nois1sc1000a ? hhc is in engineering sample. marking diagram xxxxx = specific device code a = assembly location wl = wafer lot yy = year ww = work week nnnn = serial number 53 33 12 32 74 52 75 11 84 1
nois1sm1000s, nois1sm1000a http://onsemi.com 3 introduction overview this specification details the ratings, physical, geometrical electrical and electro-optical characteristics, test and inspection data for a cmos active pixel image sensor (cmos aps) based on type star 1000. the sensor has a format of 1024 by 1024 pixels on a 15 m x 15 m pitch, and contains an on-chip 10-bit adc. this specification shall be read in conjunction with the escc generic specification escc 9020 issue 2 dated march 2010. export clearance the star1000 is subject to export clearance for some countries and applications, and an export license might be required . component type variants a summary of the type variants of the basic cmos image sensor is shown in the ordering information. the complete list of detailed specifications for each type option is listed in the acceptance criteria specification. all specifications presented in this datasheet are rated at 22 3 c, under nominal clocking and bias conditions. exceptions are noted in the ?remarks? field. soldering instructions soldering is restricted to manual soldering only. no wave or reflow soldering is allowed. for the manual soldering, following restrictions are applicable: ? solder 1 pin on each of the 4 sides of the sensor ? cool down period of min. 1 minute before soldering another pin on each of the 4 sides ? repeat soldering of 1 pin on each side, including a 1 minute cool down period. handling precautions the component is susceptible to damage by electro-static discharge. therefore, suitable precautions shall be employed for protection during all phases of manufacture, testing, packaging, shipment and any handling. the following guidelines are applicable: ? always manipulate the devices in an esd controlled environment ? always store the devices in a shielded environment that protects against esd damage (at least a non-esd generating tray and a metal bag) ? always wear a wrist strap when handling the devices and use esd safe gloves. the star1000 is classified as class 1a (jedec classification ? [ad03]) device for esd sensitivity. for proper handling and storage conditions, refer to on semiconductor application note an52561, image sensor handling and best practices. storage information the components must be stored in a dust-free and temperature-, humidity and esd controlled environment. ? devices must always be stored in special esd-safe trays such that the glass window is never touched. ? the trays are closed with eds-safe rubber bands ? the trays are sealed in an esd-safe conductive foil in clean room conditions. ? for transport and storage outside a clean room the trays are packed in a second esd-save bag that is sealed in clean room. limited warranty on image sensor business unit warrants that the image sensor products to be delivered hereunder, if properly used and serviced, will conform to seller?s published specifications and will be free from defects in material and workmanship for two (2) years following the date of shipment. if a defect were to manifest itself within two (2) years period from the sale date, on semiconductor will either replace the product or give credit for the product. return material authorization (rma) on semiconductor packages all of its image sensor products in a clean room environment under strict handling procedures and ships all image sensor products in esd-safe, clean-room-approved shipping containers. products returned to on semiconductor for failure analysis should be handled under these same conditions and packed in its original packing materials, or the customer may be liable for the product.
nois1sm1000s, nois1sm1000a http://onsemi.com 4 applicable documents the following documents form part of this specification and shall be read in conjunction with it: no. reference title issue date ad01 escc generic specification 9020 charge coupled devices, silicon, photosensitive 2.0 march 2010 ad02 cisp spec# 001-06225 electro-optical test methods for cmos image sensors e october, 2008 ad03 jesd22-a114-b electrostatic discharge (esd) sensitivity testing human body model (hbm) b june, 2000 ad04 aps-ff-sc-03-010 process identification document 3.0 ad05 cisp spec# 001-49283 visual inspection for fm devices 1 january, 2008 note: cisp # ? cmos image sensor products, on semiconductor terms, definitions abbreviations, symbols and units for the purpose of this specification, the terms, definitions, abbreviations, symbols and units specified in escc basic specification 21300 shall apply. the following formulas are applicable to convert %vsat and mv/s into e- and e-/s: ? fpn [ e ] fpn [% vsat ]* vsat conversion_gain ? dark_signal [ e s ] dark_signal [ v s ] conversion_gain ? dsnu [ e ] dsnu [% vsat ]* vsat conversion_gain ? conversion gain for star1000: 11.5 v/e-
nois1sm1000s, nois1sm1000a http://onsemi.com 5 test procedure overview environmental and endurance tests electrical and electro-optical measurements on completion of environmental test the parameters to be measured on completion of environmental tests are scheduled in table 21. unless otherwise stated, the measurements shall be performed at an environmental temperature of 22 3 c. measurements of dark current are performed at 22 1 c and the actual environmental temperature must be reported with the test results. electrical and electro-optical measurements at intermediate point during endurance test the parameters to be measured at intermediate points during endurance test of environmental tests are scheduled in table 21. unless otherwise stated, the measurements shall be performed at an environmental temperature of 22 3 c. electrical and electro-optical measurements on completion of endurance test the parameters to be measured on completion of endurance tests are scheduled in table 21. unless otherwise stated, the measurements shall be performed at an environmental temperature of 22 3 c . conditions for operating life test the conditions for operating life tests shall be as specified in table 20 of this specification. electrical circuits for operating life test circuits for performing the operating life test are shown in figure 2 of this specification. conditions for high temperature storage test the temperature to be applied shall be the maximum storage temperature specified in table 6 of this specification. lot acceptance and screening lot acceptance and screening are based on the esa basic specification escc 9020. this paragraph describes the lat and screening for the star100 0 flight model devices. table 1. wafer lot acceptance (on every fab lot) test test method number of devices test condition test location wafer processing data review pid na na on semiconductor sem escc 21400 4 devices na test house total dose test escc 22900 3 devices see below test house by on semiconductor endurance test mil-std-883 method 1005 6 devices see below test house total dose test conditions performed on unscreened devices: ? nois1sm1000s-hhc 100krad at 3.6 krad/hour max dose rate, and biased endurance test conditions performed on unscreened devices: ? nois1sm1000s-hhc 2000h, biased at +125 c
nois1sm1000s, nois1sm1000a http://onsemi.com 6 figure 2. wafer lot acceptance test (table 1) scanning electron microscope (sem) escc 21400 (4 devices) total dose radiation escc 22900 (3 devices) endurance test mil-std-883 method 1005 (3 devices) visual inspection (7 devices ? 3 from tid, 3 life, 1 spare) characterization (spectral response and pv curves) (7 devices ? 3 from tid, 3 life, 1 spare) electrical measurements (-40 c, +25 c, +85 c) (7 devices ? 3 from tid, 3 life, 1 spare) characterization (spectral response and pv curves) (3 screened devices) every wafer lot assembly wafer lot acceptance report electrical measurements (-40 c, +25 c, +85 c) (7 devices ? 3 from tid, 3 life, 1 spare) on semiconductor louvain la neuve mpd
nois1sm1000s, nois1sm1000a http://onsemi.com 7 table 2. assembly lot acceptance test test method number of devices test condition test location special assembly house in process control assembly house bond strength test mil-std-883 method 2011 2 d assembly house assembly house geometrical data review all on semi solderability mil-std883, method 2003 3 d test house terminal strength mil-std 883, method 2004 marking permanence escc 24800 geometrical measurements icd all on semi temperature cycling mil-std 883, method 1010 5 b 50 cycles ?55 c/+125 c test house moisture resistance jedec std method 1018.3 5 procedure 1 test house cycling around dew point 5 see note ** test house dpa die shear test mil-std-883 method 2019 4 n/a test house bond pull test mil-std-883 method 2011 all wires test house before and after the following tests are done: ? electrical testing at high, low and room temperature. this testing is performed in accordance with the icd. ? detailed visual inspection in accordance with cisp# spec 001-49283 ? fine leak test mil-std-883, test method 1014, condition a ? pass condition is < 5 x 10-7 atms. cm3/s ? gross leak test mil-std-883, test method 1014, condition c ? pass condition is no bubbles visible during test note: as the glass lid needs to be removed in order to perform the dpa, this test cannot be guaranteed to be 100% successful. moisture resistance: ? 240 hours at 85 c & 85% rh ** cycling around dew point ? cycling between ? 30 c and +50 c (under a non-condensing atmosphere) ? rate: 3 c/minute ? low temperature and high temperature dwell time: 3 hrs ? number of cycles: 10 ? electrical bias shall be applied: static/operational bias cycling around dew point implementation date: january 1, 2014 assembly cut off date code: 0114
nois1sm1000s, nois1sm1000a http://onsemi.com 8 figure 3. assembly lot acceptance test (table 2) electrical measurements (-40 c, +25 c, +85 c) detailed visual inspection, geometrical data (8 screened devices) temperature cycling mil-std-883 method 1010 dpa: die shear test bond pull test (4 devices) leg 1: 3 devices assembly lot acceptance report 5 devices 3 devices shipping moisture resistance jedec std method a101-b cycling around dew point see conditions visual inspection escc2059000 & vi document fine & gross leak test mil-std-883 method 1014 outgoing visual inspection escc2059000 & vi document shipping electrical measurements (-40 c, +25 c, +85 c) detailed visual inspection (leg 2: 5 screened devices) shipping solderability mil-std883, method 2003 marking permeance escc 24800 terminal strength mil-std 883, method 2004 leg 1: 2 devices leg 2: 2 devices on semiconductor rood microtec fine & gross leak test mil-std-883 method 1014
nois1sm1000s, nois1sm1000a http://onsemi.com 9 table 3. periodic testing as stated in the escc 9020, periodic testing is performed every 2 years. the following tests are part of the periodic testing. test test method number of devices test condition test location mechanical shock mil-std 883, method 2002 2 b - 5 shocks, 1500g ? 0.5 ms ? 1/2 sine, 6 axes, 30 shocks total test house mechanical vibration mil-std 883, method 2007 2 a - 4 cycles, 20g 80 to 2000 hz, 0.06 inch 20 to 80 hz, 3 axes, 12 cycles total test house dpa die shear test mil-std-883 method 2019 2 n/a test house bond pull test mil-std-883 method 2011 all wires test house before and after the mechanical testing the following testing is performed. ? electrical verification test at room temperature. ? detailed visual inspection in accordance with cisp# spec 001-49283 ? geometrical measurements ? fine leak test mil-std-883, test method 1014, condition a ? pass condition is < 5x 10-7 atms. cm 3 /s ? gross leak test mil-std-883, test method 1014, condition c ? pass condition is no bubbles visible during test note: as the glass lid needs to be removed in order to perform the dpa, this test cannot be guaranteed to be 100% successful. table 4. assembled units screening (100% coverage) test test method test condition test location electrical testing at high, low and room temperature cisp spec# 001-66578 ht +85 c lt ?40 c rt +25 c on semiconductor geometrical measurements on semiconductor visual inspection cisp spec# 001-49283 on semiconductor stabilization bake mil-std-883 method 1008 48h at 125 c test house xray escc 20900 test house fine leak test mil-std-883 method 1014 a test house gross leak test mil-std-883 method 1014 c test house temperature cycling mil-std-883 method 1010 b - 10 cycles ?55 c / +125 c test house biased burn-in 240h at +125 c. on semiconductor mobile particle detection mil-std-883 method 2020 a test house fine leak test mil-std-883 method 1014 a test house gross leak test mil-std-883 method 1014 c test house electrical testing at high, low and room temperature cisp spec# 001-66578 ht +85 c lt ?40 c rt +25 c on semiconductor final visual inspection cisp spec# 001-49283 on semiconductor
nois1sm1000s, nois1sm1000a http://onsemi.com 10 specifications table 5. acceptance criteria key specification defective pixels 20 bright pixels in fpn image 20 defective pixels in prnu image 50 defective columns 0 defective rows 0 allowed adjacent bright pixels 2 allowed cluster size of 4 or more bright pixels 0 dsnu defects @ 22 c bol 108 note: a detailed acceptance criteria specification is available upon request. table 6. minimum / maximum ratings limits characteristics min max units any supply voltage -0.5 +5 . 5 v voltage on any input terminal -0.5 vdd +0.5 v operating temperature -40 +85 c storage temperature -55 +125 c soldering temperature na 260 c note: engineering model option is guaranteed for room temperature only. note: stresses above these ratings may cause permanent damage. a 7v peak for very short durations is sustainable, but exposure t o absolute maximum conditions for extended periods may degrade device reliability. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. on semiconductor recommends that customers become familiar with, and follow the procedures in jedec standard jesd625-a. refer to application note an52561. table 7. general specifications characteristics limits image sensor format 1024 by 1024 pixels pixel size 15 m by 15 m adc resolution 10 bit table 8. mechanical specifications parameter description min typ max units die (referring to figure 5: die optical center) die thickness (applicable to star 1000 mono) 488 508 528 m die thickness (applicable to star 1000 color) 605 625 645 m flatness of the image area 10 m die center, x offset to the center of package 0.002 0.052 0.102 mm die center, y offset to the center of the package 0.1 0.2 0.3 mm die position, x tilt (-0.1) 0 (0.1) deg die position, y tilt (-0.1) 0 (0.1) deg die placement accuracy in package (-50) - (+50) m die rotation accuracy (-50) - (+50) m optical center referenced from package center (x-dir) (-50) 0 (+50) m optical center referenced from package center (y-dir) (-50) 0 (+50) m package package weight 7.7 7.85 8 g package thickness (package + epoxy + glass lid), not including lead height 3.3 3.45 3.6 mm
nois1sm1000s, nois1sm1000a http://onsemi.com 11 table 9. glass lid specifications no. characteristic min typ max unit remarks 1a xy size 26.7 x 26.7 26.8 x 26.8 26.9 x 26.9 mm 1b thickness 1.4 1.5 1.6 mm 2a spectral range for optical coating of window 440 na 1100 nm 2b reflection coefficient for window na <0.8 <1.3 % over bandwidth indicated in 2a 3 optical quality: scratch max width scratch max number dig max size dig max number n/a n/a 10 5 60 25 m total dose radiation test application the total dose radiation test shall be performed in accordance with the requirements of escc basic specification 22900. parameter drift values the allowable parameter drift values after total dose irradiation are listed in t able 17. the parameters shown are valid after a total dose of 270 krad and 168h/100 c annealing. bias conditions continuous bias shall be applied during irradiation testing as shown in figure 2 of this specification. electrical and electro-optical measurements the parameters to be measured, prior to, during and on completion of the irradiation are listed in table 21 of this specification. only devices that meet the specification in table 21 of this specification shall be included in the test sample. table 10. radiation influence characteristics limits units min typ max operating temperature range -40 na +85 c total dose radiation tolerance (device in operation) 270 na na krad (si) equivalent proton influence 2.4e 11 na na proton/cm 2 sel threshold 127.8 na na mev cm 3 mg -1
nois1sm1000s, nois1sm1000a http://onsemi.com 12 electrical and electro-optical measurements electrical and electro-optical measurements at high and low temperature the engineering model option is screened for room temp only, while the flight model option is screened over the full guaranteed temperature range. circuits for electrical and electro-optical measurements a circuit for performing the electro-optical tests shown below is shown in figure 2. table 11. electrical characteristics (under nominal bias conditions at nominal pixel rate with tj = 22 3 c in ?soft reset?, unless otherwise stated) characteristics limits units min typ max total power supply current stand-by 53.8 56.6 ma total power supply current, operational 57.4 60.8 ma power supply current to adc, operational 44.6 48 ma power supply current to image core, operational 12.8 14 ma input impedance digital input 200 k input impedance dark reference input 200 k input impedance adc input 200 k output impedance digital outputs. (note 1) 200 ? 700 output impedance analog output. (note 1) 100 output amplifier voltage range 0.5 4.5 v dark reference offset. (note 2) 0.6 0.93 v output amplifier gain setting 1. (note 3) 3.95 4.45 4.96 output amplifier gain setting 2. (note 3) 2.05 2.30 2.55 output amplifier gain setting 3. (note 3) 7.36 8.38 9.40 adc ladder network resistance 1054 1174 1295 adc ladder network temperature coefficient for temperature range ? 40 c to +85 c 4.53 / c adc differential non linearity 3.89 8.4 lsb adc integral non linearity 1.29 1.95 lsb adc set-up time to attain 1% conversion accuracy 250 ns adc delay time 72 ns v ih voltage input threshold ?high? (note 4) 2.3 vdd v v il voltage input threshold ?low? (note 4) 1 v v oh voltage output threshold ?high? (note 4) 4.25 v v ol voltage output threshold ?low? (note 4) 1 v product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 1. the output impedance varies for different digital outputs and is dependent on the metal routing, where d9 has the longest routi ng and d0 has the shortest routing, providing a typical range of 200-700 ohms inclusive of the esd resistance. 2. dark reference offset specifies the offset between the applied dark reference voltage and the actual level at the analogue ou tput terminal. specified at gain setting 0. 3. gain specification relative to gain setting 0. 4. these parameters are guaranteed by process and design and are not tested in production.
nois1sm1000s, nois1sm1000a http://onsemi.com 13 table 12. electro ? optical information (under nominal bias conditions at nominal pixel rate with tj = 22 3 c in ?soft reset?, unless otherwise stated) characteristics limits units min typ max saturation voltage output 0.99 1.11 1.24 v linear range (within 1%) 95 ke- full well charge (note 1) 135 ke- quantum efficiency x fill factor (between 450 nm and 750 nm) 30 % responsivity narrow band blue, at 475 nm 20 nm 21000 25300 adu responsivity narrow band green, at 526 nm 20 nm 20500 24800 adu responsivity narrow band red, at 630 nm 20 nm 18400 23000 adu charge to voltage conversion factor. (note 2) 11.5 mv/e- temporal noise, at 5 mhz clock rate 0.61 0.72 mv temporal noise, at 2 mhz clock rate 0.77 1.02 mv temporal noise, at 10 mhz clock rate 0.82 1.13 mv local fixed pattern noise standard deviation, at 5 mhz clock rate. (note 3) 0.13 0.20 %v sat global fixed pattern noise standard deviation, at 5 mhz clock rate. (note 4) 0.38 0.62 %v sat local fixed pattern noise standard deviation, at 2 mhz clock rate. (note 3) 0.20 0.27 %v sat global fixed pattern noise standard deviation, at 2 mhz clock rate. (note 4) 0.42 0.55 %v sat local fixed pattern noise standard deviation, at 10 mhz clock rate. (note 3) 0.21 0.33 %v sat global fixed pattern noise standard deviation, at 10 mhz clock rate. (note 4) 0.39 0.78 %v sat column fpn. (note 5) 0.37 0.61 %v sat average dark signal 13.5 28.2 mv/s dark signal temperature dependency (temperature rise for doubling average dark current) 9.2 c local dark signal non uniformity standard deviation 0.79 1.03 %v sat global dark signal non uniformity standard deviation 0.99 1.32 %v sat local photo response non uniformity, standard deviation. (note 6) 0.95 1.33 % global photo response non uniformity, standard deviation. (note 7) 3.30 6.09 % mtf x direction. (note 8) 0.26 mtf y direction. (note 8) 0.37 pixel to pixel cross talk x direction. (note 9) 17.5 % pixel to pixel cross talk y direction. (note 9) 16 % anti-blooming capability x 1000 1. full well charge and linear range are calculated from detailed electro-optical response measurements. 2. charge to voltage conversion factor is calculated from the detailed electro-optical response measurements. 3. percentage of full well charge, measured in complete fpa area. local specification indicates variation of pixel values with r espect to the average of a 20 x 20 window area. the number given is the average of all 20 x 20 window fpns. 4. percentage of full well charge, measured in complete fpa area. global specification indicates variation of pixel value with respect to globa l average. 5. percentage of full well charge, measured in the complete fpa area 6. percentage of signal (black offset subtracted), measured in complete fpa area. local specification indicates variation of pix el values with respect to the average of a 20 x 20 window area. the number given is the average of all 20 x 20 window prnus. 7. percentage of signal (black offset subtracted), measured in complete fpa area. global specification indicates variation of pi xel value with respect to global average. 8. mtf is calculated from the detailed electro-optical response measurements. 9. pixel to pixel optical crosstalk in percentage of charge in illuminated pixel.
nois1sm1000s, nois1sm1000a http://onsemi.com 14 table 13. electrical and electro ? optical measurements at reference temperature the limits in this table set the acceptance criteria for procurement of samples. characteristics limit min limit max units contact test, esd input structures no fail no fail total power supply current stand-by 56.0 ma total ps current, operational 60.1 ma ps current adc, operational 47.3 ma ps current to image core, operational 13.8 a offset 0 -100 100 mv output amplifier gain setting 1. (note 1) 4.02 5.01 output amplifier gain setting 2. (note 1) 2.07 2.58 output amplifier gain setting 3. (note 1) 7.57 9.42 adc ladder network resistance 1078 1271 adc differential non linearity na 8.36 lsb adc integral non linearity na 1.82 lsb saturation voltage output 1.01 na v responsivity narrow band blue 21900 na adu responsivity narrow band green 21400 na adu responsivity, narrow band red 19300 na adu temporal noise, nom. clock frequency 0.75 mv temporal noise, red. clock frequency 0.97 mv temporal noise, enhanced clock freq. 1.07 mv local fixed pattern noise standard deviation, at 5 mhz clock rate. (note 2) 0.22 %vsat global fixed pattern noise standard deviation, at 5 mhz clock rate. (note 3) 0.57 %vsat local fixed pattern noise standard deviation, at 2 mhz clock rate. (note 2) 0.25 %vsat global fixed pattern noise standard deviation, at 2 mhz clock rate. (note 3) 0.52 %v sat local fixed pattern noise standard deviation, at 10 mhz clock rate. (note 2) 0.34 %v sat global fixed pattern noise standard deviation, at 10 mhz clock rate. (note 3) 0.70 %v sat column fpn. (note 4) 0.56 %v sat average dark signal 25.3 mv/s local dsnu standard deviation 0.98 %v sat global dsnu standard deviation 1.26 %v sat local prnu, standard deviation. (note 5) 1.25 % global prnu, standard deviation. (note 6) 5.53 % 1. gain specification relative to gain setting 0. 2. percentage of full well charge, measured in complete fpa area. local specification indicates variation of pixel values with r espect to the average of a 20 x 20 window area. the number given is the average of all 20 x 20 window fpns. 3. percentage of full well charge, measured in complete fpa area. global specification indicates variation of pixel value with respect to globa l average. 4. percentage of full well charge, measured in the complete fpa area. 5. percentage of signal (black offset subtracted), measured in complete fpa area. local specification indicates variation of pix el values with respect to the average of a 20 x 20 window area. the number given is the average of all 20 x 20 window prnus. 6. percentage of signal (black offset subtracted), measured in complete fpa area. global specification indicates variation of pi xel value with respect to global average.
nois1sm1000s, nois1sm1000a http://onsemi.com 15 table 14. electrical and electro-optical measurements at +85 c characteristics limit min limit max units total power supply current stand-by 56.6 ma total ps current, operational 60.6 ma ps current adc, operational 47.7 ma ps current to image core, operational 13.9 a adc ladder network resistance 1341 1576 saturation voltage output 1.05 v responsivity narrow band blue 22100 adu responsivity narrow band green 21500 adu responsivity, narrow band red 19600 adu temporal noise, at 10 mhz clock rate 2.37 mv average dark signal 950 mv/s local dsnu standard deviation 1.02 %v sat global dsnu standard deviation 2.84 %v sat number of dsnu signal defects na local prnu, standard deviation. (note 3) 1.30 % global prnu, standard deviation. (note 4) 4.31 % table 15. electrical and electro-optical measurements at ? 40 c characteristics limit min limit max units total power supply current stand-by 60.0 ma total ps current, operational 63.9 ma ps current adc, operational 51.1 ma ps current to image core, operational 13.2 a adc ladder network resistance 770 1013 saturation voltage output 1.01 v responsivity narrow band blue 22100 adu responsivity narrow band green 22200 adu responsivity, narrow band red 19700 adu temporal noise, at 10 mhz clock rate . 0.60 mv local fixed pattern noise standard deviation, at 10 mhz clock rate. (note 1) 0.22 %v sat global fixed pattern noise standard deviation, at 10 mhz clock rate. (note 2) 0.41 %v sat average dark signal mv/s local dsnu standard deviation %v sat global dsnu standard deviation %v sat number of dsnu signal defects local prnu, standard deviation. (note 3) 1.25 % global prnu, standard deviation. (note 4) 5.94 % 1. percentage of full well charge, measured in complete fpa area. local specification indicates variation of pixel values with r espect to the average of a 20 x 20 window area. the number given is the average of all 20 x 20 window fpns. 2. percentage of full well charge, measured in complete fpa area. global specification indicates variation of pixel value with respect to globa l average. 3. percentage of signal (black offset subtracted), measured in complete fpa area. local specification indicates variation of pix el values with respect to the average of a 20 x 20 window area. the number given is the average of all 20 x 20 window prnus. 4. percentage of signal (black offset subtracted), measured in complete fpa area. global specification indicates variation of pi xel value with respect to global average.
nois1sm1000s, nois1sm1000a http://onsemi.com 16 table 16. electrical characteristics the min and max limits of table 3 apply table 17. parameter drift values for radiation testing at 22 1 c characteristics limits units min typ max average dark signal rise 252 424 e - /s per krad local dark signal non uniformity rise 5 10 e - /s per krad global dark signal non uniformity rise 6 14 e - /s per krad table 18. proton radiation drift values characteristics limits units min typ max average dark signal, at 22 1 c 35 mv/s local dark signal non uniformity standard deviation 2.5 % global dark signal non uniformity standard deviation 2.7 % table 19. conditions for high temperature reverse bias burn ? in not applicable table 20. conditions for power burn-in and operating life tests characteristics symbol test condition units ambient temperature tamb 125c c all power supplies vdd +5.5 v bias conditions see figure 2 x clock frequency 5 mhz
nois1sm1000s, nois1sm1000a http://onsemi.com 17 table 21. electrical and electro-optical measurements on completion of environmental tests and at intermediate points and on completion of endurance testing characteristics limit min limit max units contact test, esd input structures no fail no fail total power supply current stand-by 56.0 ma total ps current, operational 60.1 ma ps current adc, operational 47.3 ma ps current to image core, operational 13.8 a offset 0 -100 100 mv output amplifier gain setting 1. (note 1) 4.02 5.01 output amplifier gain setting 2. (note 1) 2.07 2.58 output amplifier gain setting 3. (note 1) 7.57 9.42 adc ladder network resistance 1078 1271 adc differential non linearity 8.36 lsb adc integral non linearity 1.82 lsb saturation voltage output 1.01 v responsivity narrow band blue 21900 adu responsivity narrow band green 21400 adu responsivity, narrow band red 19300 adu temporal noise, at 5 mhz clock rate 0.75 mv temporal noise, at 2 mhz clock rate 0.97 mv temporal noise, at 10 mhz clock rate 1.07 mv local fixed pattern noise standard deviation, at 5 mhz clock rate. (note 2) 0.22 %v sat global fixed pattern noise standard deviation, at 5 mhz clock rate. (note 3) 0.57 %v sat local fixed pattern noise standard deviation, at 2 mhz clock rate. (note 2) 0.25 %v sat global fixed pattern noise standard deviation, at 2 mhz clock rate. (note 3) 0.52 %v sat local fixed pattern noise standard deviation, at 10 mhz clock rate. (note 2) 0.34 %v sat global fixed pattern noise standard deviation, at 10 mhz clock rate. (note 3) 0.70 %v sat column fpn. (note 4) 0.56 %v sat average dark signal 25.3 mv/s local dsnu standard deviation 0.98 %v sat global dsnu standard deviation 1.26 %v sat local prnu, standard deviation . (note 5) 1.25 % global prnu, standard deviation. (note 6) 5.53 % 1. gain specification relative to gain setting 0. 2. percentage of full well charge, measured in complete fpa area. local specification indicates variation of pixel values with r espect to the average of a 20 x 20 window area. the number given is the average of all 20 x 20 window fpns. 3. percentage of full well charge, measured in complete fpa area. global specification indicates variation of pixel value with respect to globa l average. 4. percentage of full well charge, measured in the complete fpa area. 5. percentage of signal (black offset subtracted), measured in complete fpa area. local specification indicates variation of pix el values with respect to the average of a 20 x 20 window area. the number given is the average of all 20 x 20 window prnus. 6. percentage of signal (black offset subtracted), measured in complete fpa area. global specification indicates variation of pi xel value with respect to global average.
nois1sm1000s, nois1sm1000a http://onsemi.com 18 table 22. expected electrical and electro-optical measurements during and after total-dose irradiation testing total-dose irradiation testing performed as part of the qualification campaign. total-dose testing is not part of the productio n testing. characteristics limit max units total power supply current stand-by 56.0 ma total ps current, operational 60.1 ma local fixed pattern noise standard deviation, at 5 mhz clock rate. (note 1) 0.22 %v sat global fixed pattern noise standard deviation, at 5 mhz clock rate. (note 2) 0.57 %v sat number of fpn signal defects table 17 average dark signal table 17 local dsnu standard deviation table 17 global dsnu standard deviation table 17 table 23. expected power and electro-optical measurements during and after proton irradiation testing proton irradiation testing performed as part of the qualification campaign. proton testing is not part of the production testin g. test conditions: 2.4e11 protons at energy of 60 mev. characteristics limit max units total power supply current stand-by 56.0 ma total ps current, operational 60.1 ma local fixed pattern noise standard deviation, at 5 mhz clock rate. (note 1) 0.22 %v sat global fixed pattern noise standard deviation, at 5 mhz clock rate. (note 2) 0.57 %v sat number of fpn signal defects table 5 average dark signal table 17 local dsnu standard deviation table 17 global dsnu standard deviation table 17 1. percentage of full well charge, measured in complete fpa area. local specification indicates variation of pixel values with r espect to the average of a 20 x 20 window area. the number given is the average of all 20 x 20 window fpns. 2. percentage of full well charge, measured in complete fpa area. global specification indicates variation of pixel value with r espect to global average. table 24. expected power measurements during and after heavy ion irradiation testing characteristics limit min limit max units total power supply current stand-by 56.0 ma total ps current, operational 60.1 ma ion irradiation testing performed as part of the qualification campaign. ion irradiation testing is not carried out on every wafer lot. test conditions: sensor operated at nominal speed with monitoring of power supply current. heavy ion testing performed with a total dose of 10e7 particles with an effective let of 127.8 mev/mg/cm 2 . burn ? in test parameter drift values the parameter drift values for power burn-in are specified in table 13 of this specification. unless otherwise specified the measurements shall be conducted at an environmental temperature of 22 3 c and under nominal power supply, bias and timing conditions. the parameter drift values ( ) shall not be exceeded. in addition to these drift value requirements, also the limit values of any parameter as indicated in table 13 shall not be exceeded. conditions for high temperature reverse bias burn-in not applicable conditions for power burn-in the conditions for power burn-in shall be as specified in table 20 of this specification electrical cir cuits for high temperature reverse bias burn-in not applicable electrical circuits for power burn-in circuits to perform the power burn-in test are shown in figure 2 of this specification.
nois1sm1000s, nois1sm1000a http://onsemi.com 19 figure 4. star1000 functional diagram (used for biasing, burn in, life and electro optical measurements)
nois1sm1000s, nois1sm1000a http://onsemi.com 20 mechanical specifications dimension check the dimensions of the components specified herein shall be checked. they shall comply with the specifications and the tolerances as indicated in figure 3 and in section package dimensions on page 21. geometrical characteristics the geometrical characteristics of the components specified herein shall be checked. they shall comply with the specifications and the tolerances as indicated in section package dimensions on page 21. weight the maximum weight of the components specified herein shall be as specified in table 8. materials and finishes the materials and finishes shall be as specified herein. where a definite material is not specified, a material which will enable the components specified herein to meet the performance requirements of this specification shall be used. case the case shall be hermetically sealed and have a ceramic body and a glass window. type jlcc-84 material black alumina ba-914 thermal expansion coefficient 7.6 x 10 -6 /k hermeticity < 5 x 10e-7 atm cc/s thermal resistance (junction to case) 3.633 c/w lead material and finish lead material kovar 1e finish nickel, min 2 m 2 nd finish gold, min 1.5 m window the window material shall be bk7g18 with anti-reflective coating applied on both sides. the window has a coating free border of 1.5 mm on both sides at each border. refer to table 8 for the anti ? reflective coating specification and table 9 for the glass defect criteria. a detailed drawing of the window is given in figure 3.
nois1sm1000s, nois1sm1000a http://onsemi.com 21 figure 5. die optical center 200 x y center of cavity and of fpa center of silicium offset between center of silicium and center of cavity: x: 52 m 52 parallelism in x and y within + 50 mm pin 1 a a
nois1sm1000s, nois1sm1000a http://onsemi.com 22 figure 6. glass lid dimensions
nois1sm1000s, nois1sm1000a http://onsemi.com 23 package dimensions jldcc84 case 114ak issue a
nois1sm1000s, nois1sm1000a http://onsemi.com 24 pin description this appendix contains a pin description for the star1000 cmos image sensor . table 25. pin list pin pin name pin type pin description 1 a3 input 2 a4 input 3 a5 input 4 a6 input 5 a7 input 6 a8 input 7 a9 input 8 ld_y input digital input. latch address (a0 ? a9) to y-register (0 = track, 1 = hold). 9 ld_x input digital input. latch address (a0 ? a9) to x-register (0 = track, 1 = hold). 10 vdda supply analog power supply of the imager (typical 5 v). 11 gndd ground digital ground of the imager. 12 gnda ground analog ground of the imager. 13 clk_x input digital input. clock x-register (output valid & stable when clk_x is high). 14 reset_ds input digital input (active high). resets row indicated by y-address (see sensor timing diagram). reset_ds is used for dual-slope integration (see faq). gnd is used for normal operation. 15 vddd supply digital supply of the image sensor. 16 reset input digital input (active high). resets row indicated by y-address (see sensor timing diagram). 17 s input digital input (active high). control signal for column amplifier (see sensor timing diagram). 18 r input digital input (active high). control signal for column amplifier (see sensor timing diagram). 19 nbias_dec input analog input. biasing of address decoder. connect with 100 k to vdda and decouple with 100 nf to gnd. 20 a_in2 input additional analog inputs. for proper conversion with on-chip adc, the input signal must lie within the output signal range of the image sensor (approxim- ately +2 v to +4 v). 21 a_in3 input 22 a_in1 input 23 a_sel1 input selection of analog channel: ?00? selects image sensor (?01? selects a_in1, ?10? a_in2, and ?11? a_in3). 24 a_sel0 input 25 nbias_oamp input analog input. bias of output amplifier (speed/power control). connect with 100 k to vdda and decouple with 100 nf to gnd for 12.5 mhz output rate (lower resistor values yield higher maximal pixel rates at the cost of extra power dissipation). 26 pbias input analog input. biasing of the multiplexer circuitry. connect with 20 k to gnd and decouple with 100 nf to vdd. 27 g1 input digital input. select output amplifier gain value: g0 = lsb, g1 = msb (?00? = unity gain, ?01? = x2, ?10? = x4, ?11? = x8). 28 g0 input 29 cal input digital input (active high). initialization of output amplifier. output amplifier outputs blackref in unity gain mode when cal is high (1). apply pulse pattern (see sensor timing diagram). 30 out output analog output video signal. connected to the analog input of the internal (pin 52) 10-bit adc or an external adc.
nois1sm1000s, nois1sm1000a http://onsemi.com 25 table 25. pin list pin pin description pin type pin name 31 blackref input analog input. control voltage for output signal offset level. buffered on-chip, the reference level can be generated by a 100 k resistive divider. connect to 2 v dc for use with on-chip adc. 32 vdda supply analog power supply of image core (typical 5 v). 33 vddd supply digital power supply of image core (typical 5 v). 34 gnda ground analog ground of image core. 35 gndd ground digital ground of image core. 36 nbias_array input analog input. biasing of the pixel array. connect with 1m to vdda and de- couple with 100 nf capacitor to gnd. 37 nc pins 37 through 47 are no connects. 38 nc 39 nc 40 nc 41 nc 42 nc 43 nc 44 nc 45 nc 46 nc 47 nc 48 testpixarray output analog output of an array of 20 x 35 test pixels where all photodiodes are connected in parallel. is used for electro-optical evaluation. 49 photodiode output plain photo diode (without circuitry). area of the photodiode = 20 x 35 pixels. is used for electro-optical evaluation. 50 nbias_ana input analog input. analog biasing of the adc circuitry. connect with 100 k to vdda and decouple with 100 nf to gnd. 51 nbias_ana2 input 52 in_adc input analog input of the internal adc. connect to analog output of image sensor (pin 30). input range (typically 2 v and 4 v) of the internal adc is set between by vlow_adc (pin 55) and vhigh_adc (pin 62). 53 vdd_adc_ana supply analog power supply of the adc (typical 5 v). 54 gnd_adc_ana ground analog ground of the adc. 55 vlow_adc input low reference voltage of internal adc. nominal input range of the adc is between 2 v and 4 v. the resistance between vlow_adc and vhigh_adc is approximately 1.5 k . connect with 1.5 k to gnd and decouple with 100 nf to gnd. 56 nc 57 pbiasdig2 input connect with 20 k to gnd and decouple with 100 nf to vdda. 58 bitinvert input digital input. inversion of the adc output bits. 0 = invert output bits (0 => black, 1023; white, 0), 1 = no inversion of output bits (black, 0; white, 1023). 59 tri_adc input digital input. tri-state control of digital adc outputs (1 = tri-state, 0 = normal mode). 60 d0 input adc output bits.#d0 = lsb, d9=msb. 61 clk input digital input. adc clock. adc converts on falling edge. 62 vhigh_adc input high reference voltage of internal adc. nominal input range of the adc is between 2 v and 4 v. the resistance between vlow_adc and vhigh_adc is about 1.5 k . connect with 1.1 k to vdda and decouple with 100 nf to gnd.
nois1sm1000s, nois1sm1000a http://onsemi.com 26 table 25. pin list pin pin description pin type pin name 63 gnd_adc_ana ground analog ground of the adc circuitry. 64 vdd_adc_ana supply analog supply of the adc circuitry (typical 5 v). 65 vdd_adc_dig supply digital supply of the adc circuitry (typical 5 v). 66 gnd_adc_dig output digital ground of the adc circuitry. 67 vdd_dig_out supply power supply of adc digital output. connect to 5 v for normal operation. can be brought to lower voltage when image sensor must be interfaced to low voltage periphery. 68 d1 output adc output bits. #d0 = lsb, d9 = msb. 69 d2 output 70 d3 output 71 d4 output 72 d5 output 73 vdda supply analog supply of the image core (typical 5 v). 74 gnda ground analog ground of the image core (typical 5 v). 75 gnd_ab supply anti-blooming drain control voltage. default: connect to ground where the anti-blooming is operational but not maximal. apply 1 v dc for improved anti-blooming. 76 vref supply analog supply. reset level for reset_ds. is used for extended optical dynamic range. see faq for more details. 77 vres supply analog supply. reset level for reset (typical 5 v). 78 d6 output adc output bits. #d0 = lsb, d9 = msb. 79 d7 output 80 d8 output 81 d9 output 82 a0 input digital input. address inputs for row and column addressing. a9 = lsb, a0 = msb. 83 a1 input 84 a2 input
nois1sm1000s, nois1sm1000a http://onsemi.com 27 architecture floor plan the image sensor contains five sections: the pixel array, the x- and y- addressing logic, the column amplifiers, the output amplifier and the adc. figure 4 shows an outline diagram of the sensor, including an indication of the main control signals. the following paragraphs explain the function and operation of the dif ferent imager parts in detail. figure 7. image sensor architecture reset reset_ds vref ld_y a0....a9 latch y address 1024 rst 1024 rd 10 rst rd col 10-bit adc 10 d0...d9 clk_adc ain column amplifiers 1024 1024 1024 10 10 clk_x latch ld_x x register x address decoder rst sig progr. gain amplifier multiplexer buffer aout blackref cal g0f g1 ain1 ain2 ain3 sel0 sel1 1024 1024 decoder and logic pixel array 1024 x 1024 pixels s r pixel array the pixel array contains 1024 by 1024 active pixels at 15 mm pitch. each pixel contains one photo diode and three transistors as shown in figure 5. the photo diode is always in reverse bias. at the beginning of the integration cycle, a pulse is applied to the reset line (gate of t1) bringing the cathode of d1 to the reset voltage level. during the integration period, photon-generated electrons accumulate on the diode capacitance reducing the voltage on the gate of t2. the real illumination dependent signal is the difference between the reset level and the output level after integration. this difference is created in the column amplifiers. t2 acts as a source follower and t3 allows connection of the pixel signal (reset level and output level) to the vertical output bus. the reset lines and the read lines of the pixels in a row are connected together to the y- decoder logic; the outputs of the pixels in a column are connected together to a column amplifier. figure 8. 3t pixel architecture t1 t2 t3 read column bus reset
nois1sm1000s, nois1sm1000a http://onsemi.com 28 addressing logic the addressing logic allows direct addressing of rows and columns. instead of the one-hot shift registers that are often used, address decoders are implemented. one can select a line by presenting the required address to the address input of the device and latching it to the y- decoder logic. presenting the x- address to the device address input and latching it to the x- address decoder can select a column. a typical line read out sequence first selects a line by applying the y-address to the y-decoder. activation of the ld_y input on the y -logic connects the pixel outputs of the selected line to the column amplifiers. the individual column amplifier outputs are connected to the output amplifier by applying the respective x- addresses to the x- address decoder. applying the appropriate y- address to the y- decoder and activating the ?reset? input reset a line. the integration time of a row is the time between the last reset of this row and the time when it is selected for read out. the y- decoder logic has two different reset inputs: reset and reset_ds. activation of reset resets the pixel to the vdd level; activation of reset_ds resets the pixel to the voltage level on the vref input. this feature allows the application of the so called dual slope in tegration. if dual slope integration is not needed, vref is tied to vdd and reset_ds must never be activated. column amplifiers all outputs from the pixels in a column are connected in parallel to a column amplifier. this amplifier samples the output voltage and the reset level of the pixel whose row is selected at that moment and presents these voltage levels to the output amplifier. as a result, the pixels are always reset immediately after read out as part of the sample procedure. note that the maximum integration time of a pixel is the time between two read cycles. output amplifier and analog multiplexer the output amplifier combines subtraction of pixel signal level from reset level with a programmable gain amplifier. because the amplifier is ac coupled, it also contains a provision to maintain and restore the proper dc level. an analog signal multiplexing feeds the pixel signal to the final unity gain buffer, providing the required drive capability. apart from the pixel signal, three other external analog signals can be fed to the output buffer. all these signals can be digitalised by the on-chip adc if the output of this buffer is externally connected to the input of the adc. the purpose of the additional analog inputs (a_in1, a_in2, and a_in3) is to allow the possibility of processing other analog signals through the image sensors signal path. these signals can then be converted by the adc and processed by the image controller fpga. the additional analog inputs are intended for low frequency or dc signals and have a reduced bandwidth compared with the image signal path. adc the image sensor has a 10-bit adc that is electrically separated from the rest of the image sensor circuits and can be powered down if an external adc is used. the conversion takes place at the falling edge of the clock and the output pins can be disabled to allow operation of the device in a bus structure. bayer pattern the star1000 is available in a color variant. looking from top view, with pin 1 left center, pixel red is (0,0) as shown in figure 6. figure 9. bayer pattern for star1000 x_readout direction y_readout direction top view star1000 pixel array g (0,1) b (1,1) r (0,0) g (1,0)
nois1sm1000s, nois1sm1000a http://onsemi.com 29 timing and control signals the pixels addressing is done by direct addressing of rows and columns. this approach has the advantage of full flexibility when accessing the pixel array: multiple windowing and subsampled read out are possible by proper programming. the following paragraphs clarify the timing for row and column readout. row selection and reset timing figure 7 shows the timing of the line sequence control signals. the timing constraints are presented in table 26. the address, presented at the address io pins is latched in with the ld-y pulse. after latching, the external controller already produces a new address. figure 10. line selection and reset sequence a0......a9 ld_y internal s reset r cal (once each frame) row readout read address reset address k l m k l m row selected for readout row selected for reset a b c d e b h f d g time available for readout of row y-1 idle time available for x-readout of row y i latching in a y- address selects the addressed row and connects the pixel outputs of that row to the column amplifiers. through the sequence of the s and r pulse and the reset pulse in between the pixel output signal and reset level are sampled and produced at the output of the column amplifier. at this time horizontal read out of the selected row is started and another row is reset to effectuate reduced integration time. below table shows the timing constraints for the horizontal or line-select timing. the given data are based upon the results of simulations.
nois1sm1000s, nois1sm1000a http://onsemi.com 30 table 26. timing constraints of line sequence symbol min typ description a 3.6 s delay between selection of a new row and falling edge on s. minimal value: for maximum, speed a new row can already be selected during x- read out of the previous row. b 0.4 s duration of s and r pulse. c 0 100 ns delay between falling edge of s and rising edge of reset. d 200 ns minimum duration of reset pulse. e 1.6 s delay between falling edge of reset and falling edge of r. f 0 100 ns minimum delay between falling edge on ld_y and rising edge of reset. g g minimum required extension of y- address after falling edge of reset pulse. h 100 ns 200 ns position of cal pulse after rising edge of s. the cal pulse must only be given once per frame. i 100 ns 1 s duration of cal pulse. k 10 ns address set up time. l 20 ns load register value. m 10 ns address stable after load. pixel read out timing figure 8 shows the timing of the pixel readout sequence. the external digital controller presents a column address that is latched by the rising edge of the ld_x pulse. after decoding the x- address the column selection is clocked in the x- register by clk-x. the output amplifier uses the same pulse to subtract the pixel output level from the pixel reset level and the signal level. this causes a pipeline effect such that the analog output of the first pixel is effectively present at the device output terminal at the third rising edge of the x-clk signal. the adc conversion starts at the falling edge of the clk-adc signal and produces a valid digital output 20 ns after this edge. the timing constraints are given in table 27. important note: the values of the x shift-register tend to leak away after a while. therefore, it is very important to keep the clk_x signal asserted for as long as the sensor is powered up. if the sensor sits idle and clk_x is not asserted, the leakage of the x shift-register causes multiple columns to be selected at once. this forces high current through the sensor and may cause damage.
nois1sm1000s, nois1sm1000a http://onsemi.com 31 figure 11. column selection and read out sequence x1 x6 x5 x7 x8 x4 x3 x2 b a c x4 x1 x1 x2 x3 x4 x5 x6 a0......a9 ld_x clk_x analog output clk_adc d9......d0 undefined output level row idle time x2 x3 table 27. timing constraints of column read out symbol min typ description a 20 ns address setup time b 40 ns address valid time c 0 20 ns adc output valid after falling edge of clk_adc
nois1sm1000s, nois1sm1000a http://onsemi.com 32 appendix a: typical spectral response data the following figure shows a typical spectral response curve. the fringes in the curve result from optical interference in the top dielectric layers. figure 12. spectral response 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 400 wavelenght [nm] spectral r esponse [ a/w] qe 0 . 0 1 qe 0.05 qe 0 . 1 qe 0 . 2 qe 0 . 3 500 600 700 800 900 1000 0 figure 13. photovoltaic response 0 0,2 0,4 0,6 0,8 1 1,2 0?20000?40000?60000?80000100000120000140000160000180000 number of electrons voltage swing at output [v]
nois1sm1000s, nois1sm1000a http://onsemi.com 33 appendix b: typical pixel profile data figure 14. vertical pixel profile measurement data at 600 nm. figure 15. horizontal pixel profile measurement data at 600 nm.
nois1sm1000s, nois1sm1000a http://onsemi.com 34 appendix c: observed effects during annealing after total dose irradiation figure 16. star1000 average dark current during annealing figure 17. star1000 dark signal non uniformity (dsnu) during annealing average dark current rise during annealing. on the average, the dark current still increases during annealing. this observation is not in line with the conclusions of j. bogaerts. however, during this test the samples were annealed under bias while in the first test the samples were annealed without bias.
nois1sm1000s, nois1sm1000a http://onsemi.com 35 average dark current rise under annealing 221 e-/s per krad maximum dark current rise under annealing 183 e-/s per krad the average dsnu remains constant during annealing. it was observed that the average dsnu slightly rises during annealing at room temperature, immediately after irradiation but decreases at elevated temperature. the net effect is almost constant. average dsnu rise during annealing 2 e-/s per krad maximum-dsnu rise during annealing -2 e-/s per krad (see note) note: the spread in dsnu between samples decreases during annealing at temperature. appendix d: acronyms acronym description adc analog-to-digital converter afe analog front end bl black pixel data cdm charged device model cds correlated double sampling cmos complementary metal oxide semiconductor crc cyclic redundancy check dac digital-to-analog converter ddr double data rate dft design for test dnl differential nonlinearity ds double sampling dsnu dark signal nonuniformity eia electronic industries alliance esd electrostatic discharge fe frame end ff fill factor fot frame overhead time fpga field programmable gate array fpn fixed pattern noise fps frames per second fs frame start hbm human body model img regular pixel data inl integral nonlinearity acronym description ip intellectual property le line end ls line start lsb least significant bit lvds low-voltage differential signaling mbs mixed boundary scan msb most significant bit pga programmable gain amplifier pls parasitic light sensitivity prbs pseudo-random binary sequence prnu pixel random nonuniformity qe quantum efficiency rgb red green blue rma return material authorization rms root mean square roi region of interest rot row overhead time s/h sample and hold snr signal-to-noise ratio spi serial peripheral interface tbd to be determined tia telecommunications industry association t j junction temperature tr training pattern % rh percent relative humidity
nois1sm1000s, nois1sm1000a http://onsemi.com 36 appendix e: glossary conversion gain a constant that converts the number of electrons collected by a pixel into the voltage swing of the pixel. con- version gain = q/c where q is the charge of an electron (1.602e 19 coulomb) and c is the capacitance of the photodiode or sense node. dnl differential nonlinearity (for adcs) dsnu dark signal nonuniformity. this parameter characterizes the degree of nonuniformity in dark leakage currents, which can be a major source of fixed pattern noise. fill-factor a parameter that characterizes the optically active percentage of a pixel. in theory, it is the ratio of the actual qe of a pixel divided by the qe of a photodiode of equal area. in practice, it is never measured. inl integral nonlinearity (for adcs) ir infrared. ir light has wavelengths in the approximate range 750 nm to 1 mm. lux photometric unit of luminance (at 550 nm, 1lux = 1 lumen/m 2 = 1/683 w/m 2 ) pixel noise variation of pixel signals within a region of interest (roi). the roi typically is a rectangular portion of the pixe l array and may be limited to a single color plane. photometric units units for light measurement that take into account human physiology. pls parasitic light sensitivity. parasitic discharge of sampled information in pixels that have storage nodes. prnu photo-response nonuniformity. this parameter characterizes the spread in response of pixels, which is a source of fpn under illumination. qe quantum efficiency. this parameter characterizes the effectiveness of a pixel in capturing photons and con- verting them into electrons. it is photon wavelength and pixel color dependent. read noise noise associated with all circuitry that measures and converts the voltage on a sense node or photodiode into an output signal. reset the process by which a pixel photodiode or sense node is cleared of electrons. ?soft? reset occurs when the reset transistor is operated below the threshold. ?hard? reset occurs when the reset transistor is operated above threshold. reset noise noise due to variation in the reset level of a pixel. in 3t pixel designs, this noise has a component (in units of volts) proportionality constant depending on how the pixel is reset (such as hard and soft). in 4t pixel designs, reset noise can be removed with cds. responsivity the standard measure of photodiode performance (regardless of whether it is in an imager or not). units are typically a/w and are dependent on the incident light wavelength. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. roi region of interest. the area within a pixel array chosen to characterize noise, signal, crosstalk, and so on. the roi can be the entire array or a small subsection; it can be confined to a single color plane. sense node in 4t pixel designs, a capacitor used to convert charge into voltage. in 3t pixel designs it is the photodiode itself. sensitivity a measure of pixel performance that characterizes the rise of the photodiode or sense node signal in volts upon illumination with light. units are typically v/(w/m 2 )/sec and are dependent on the incident light wavelength. sensitivity measurements are often taken with 550 nm incident light. at this wavelength, 1 683 lux is equal to 1 w/m 2 ; the units of sensitivity are quoted in v/lux/sec. note that responsivity and sensitivity are used interchangeably in image sensor characterization literature so it is best to check the units. spectral response the photon wavelength dependence of sensitivity or responsivity. snr signal-to-noise ratio. this number characterizes the ratio of the fundamental signal to the noise spectrum up to half the nyquist frequency. temporal noise noise that varies from frame to frame. in a video stream, temporal noise is visible as twinkling pixels.
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